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all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. do c . ve rs i o n 0 . 5 to ta l p a g e s 3 1 da t e 2 0 0 8 / 5 / 1 9 note: the content of this speci fica tion is subject to change. model name: a030fl01 v0 product specification 3.0 color tft-lcd module < >preliminary specification < >final specification ? 2008 au optronics a ll rights reserved. do not copy www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. record of revision version revise date page content 0 19/dec/2006 first draft. 0.1 29/dec/2006 4 6 9 10-11 22-26 31 update module outline drawing. correct pin37 definition. update led current. update application circuit, add internal led driving function. update r10~r13 register setting description. add figure of packing form. 0.2 02/apr/2007 4 9 10-11 13 18 27 28 update module outline drawing. correct note1 for four leds type. update r4 value. correct min cycle setting value of 1 line scanning time. add r64, r66, r68 setting. update suggested serial command settings. update contrast ratio and white chromaticity. 0.3 08/jun/2007 4 updat e module outline with conductive tape, and change printing barcode. 0.3a 23/jul/2007 4 mark pin 1, 35, 36, 70 location in fpc connector. define thickness of fpc + stiffener. 0.4 16/oct/2007 4 to add two inter protrusions on each long site of upper bezel, and to remove al tape on bezel. 0.5 19/may/2008 5 add board-to-board connetor type www.datasheet.co.kr datasheet pdf - http://www..net/
version: 0.5 page: 1 / 31 all rights strictly reserved. any portion of this pap er shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. contents general description 2 features 2 1. general information 3 2. electrical specifications 5 2.1 fpc p in a ssignment 5 2.2 a bsolute m aximum r atings 8 3. electrical characteristics 8 3.1 tft- lcd t ypical o peration c ondition 8 3.2 b acklight d riving c onditions 9 3.3 s uggested a pplication c ircuit 10 3.3.1 s uggested a pplication c ircuit 10 3.3.2 s uggested a pplication c ircuit 11 3.4 ac t iming 12 3.4.1 t iming d iagram 12 3.4.2 t iming c ondition 13 3.5 p ower o n /o ff s equence 13 3.5.1 p ower -o n (d isplay on; s tandby d isabling ) 13 3.5.2 p ower -o ff (d isplay o ff ; s tandby e nabling ) 15 3.5.3 l ow - voltage r eset 16 3.6 s erial c ontrol s etting 17 3.6.1 i nput timing specifications ( refer to f ig . 1) 17 3.6.2 s erial setting table 18 4. optical specificationn 28 5. absolute ratings of ambient environment 30 6. packing form 31 www.datasheet.co.kr datasheet pdf - http://www..net/
version: 0.5 page: 2 / 31 all rights strictly reserved. any portion of this pap er shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. general description a030fl01 v0 is a color tft (thin film transistor) l cd (liquid crystal display). this model is composed of tft-lcd, drive ic, fpc (f lexible printed circuit), backlight unit. features 3-inch display size qqhdtv resolution and wide aspect ratio 16.7m colors system integration timing controller charge pump for vgh, vgl 2-in-1 fpc b-to-b connector sync input mode parallel digital 8-bit data interface atr-mva ( a dvanced tr ansflective C m ulti-domain v ertical a lignment) wide view angle no gray scale inverison sunlight readable high contrast ratio green design www.datasheet.co.kr datasheet pdf - http://www..net/
version: 0.5 page: 3 / 31 all rights strictly reserved. any portion of this pap er shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. 1. general information no. item unit specification remark 1 display resolution dot 480rgb(h) 272(v) 2 active area mm 65.52(h) 37.128(v) 3 screen size inch 3.0 (diagonal) 4 dot pitch mm 0.0455(h) 0.1365(v) 5 color configuration -- r. g. b. stripe note 1 6 color depth -- 16.7m colors note 2 7 overall dimension mm 76.12(h) 43.8(v) 2.5(t) note 3 8 weight g 18.8 (typical) 9 display mode -- normally black note 1: below figure shows dot stripe arrangement. note 2: the full color display depends on 8-bit data signal (pin9~34). note 3: not include fpc. refer next page to get further information. www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this pa per shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. o utline d imension of a030fl01 v0 m odule www.datasheet.co.kr datasheet pdf - http://www..net/
version: 0.5 page: 5 / 31 all rights strictly reserved. any portion of this pap er shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. 2. electrical specifications 2.1 fpc pin assignment connector: kyocera 20-5602-070-000-829 pin no symbol type description remark 1 vdd2 p power setting capacitor 2 vdda p power setting capacitor 3 gnd p ground 4 gnd p ground 5 vdd p power supply for charge pump 6 vdd p power supply for charge pump 7 vddio p power supply for digital interface 8 vdd_25v p power setting capacitor 9 r0 i red data (lsb) 10 r1 i red data 11 r2 i red data 12 r3 i red data 13 r4 i red data 14 r5 i red data 15 r6 i red data 16 r7 i red data (msb) 17 gnd p ground 18 g0 i green data (lsb) 19 g1 i green data 20 g2 i green data 21 g3 i green data 22 g4 i green data 23 g5 i green data 24 g6 i green data 25 g7 i green data (msb) www.datasheet.co.kr datasheet pdf - http://www..net/
version: 0.5 page: 6 / 31 all rights strictly reserved. any portion of this pap er shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. pin no symbol type description remark 26 gnd p ground 27 b0 i blue data (lsb) 28 b1 i blue data 29 b2 i blue data 30 b3 i blue data 31 b4 i blue data 32 b5 i blue data 33 b6 i blue data 34 b7 i blue data (msb) 35 gnd p ground 36 vcom i common voltage 37 drv o vled boost transistor driving signal 38 n/a 39 vled- p led cathode 40 vled+ p led anode 41 n/a 42 cs i serial command enable signal 43 sda i/o serial command data input 44 scl i serial command clock input 45 vsync i vertical sync signal 46 hsync i horizontal sync signal 47 grb i global reset 48 dclk i pixel clock 49 v1 p connect capacitor for power circuit 50 v2 p connect capacitor for power circuit www.datasheet.co.kr datasheet pdf - http://www..net/
version: 0.5 page: 7 / 31 all rights strictly reserved. any portion of this pap er shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. pin no symbol type description remark 51 v3 p connect capacitor for power circuit 52 v4 p connect capacitor for power circuit 53 v5 p connect capacitor for power circuit 54 v6 p connect capacitor for power circuit 55 vdd3 p power setting capacitor 56 vcl p power setting capacitor 57 vlout3 p power setting capacitor 58 v7 p connect capacitor for power circuit 59 v8 p connect capacitor for power circuit 60 v9 p connect capacitor for power circuit 61 v10 p connect capacitor for power circuit 62 v11 p connect capacitor for power circuit 63 v12 p connect capacitor for power circuit 64 vlout2 p power setting capacitor 65 vgh p power setting capacitor 66 vgl p power setting capacitor 67 vcomh p power setting capacitor for vcom 68 vcoml p power setting capacitor for vcom 69 frp o frame polarity 70 vcom i common voltage note 1: i: input; o: output; p: power. www.datasheet.co.kr datasheet pdf - http://www..net/
version: 0.5 page: 8 / 31 all rights strictly reserved. any portion of this pap er shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. 2.2 absolute maximum ratings item symbol condition min. max. unit remark vdd gnd=0 -0.3 4.5 v note 1 power voltage vddio gnd=0 -0.3 4.5 v note 1 operating temperature topa 0 60 ambient temperature storage temperature tstg -25 80 ambient temperature note 1: functional operation should be restricted under normal ambient temperature. 3. electrical characteristics the following items are measured under stable condi tion and suggested application circuit. 3.1 tft- lcd typical operation condition item symbol min. typ. max. unit remark vdd 3.1 3.3 3.5 v power supply vddio 1.65 3.3 3.5 v vsync frequency f v 60 hz hsync frequency f h 17.16 khz main frequency f dclk 9.0 10.0 mhz note 1: above every operation range is based on stable operation from suggested application circuit 3.3.1. note 2: a built-in power-on reset circuit for vdd and vddio is provided within the integrated lcd driver ic. the lcd module is in default in power save mode, and a standby releasing is required after vddio power on through serial control interface. please refer to the serial control interface for detail. note 3: the power supply of digital interface, vddio, is for the 1.8v digital inter face requirement in the future. these digital signals are dclk, hsync, vsync, r7~r0, g7~g0, b7~b0. if the digital interface is in the level of 3.3v, please short the power pin, v dd and www.datasheet.co.kr datasheet pdf - http://www..net/
version: 0.5 page: 9 / 31 all rights strictly reserved. any portion of this pap er shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. vddio, to 3.3v. in other words, no matter the voltage level of vddio is 1.65v or 3.5v , the voltage level of vdd needs to be kept around 3.3v. 3.2 backlight driving conditions parameter symbol min. typ. max. unit remark led current i l --- 20 25 ma single seral led voltage v l --- 12.8 --- v single seral led life time l l 10,000 --- --- hr note 2, 3 note 1: led backlight is four leds serial type. note 2 :define led lifetime: brightness is decreased to 50% of the initial value . led lifetime is restricted under normal condition, ambient temperature = 25 and led current = 20ma. note 3: if it uses larger led current i l more than 20ma, it maybe decreases the led lifetime. www.datasheet.co.kr datasheet pdf - http://www..net/
version: 0.5 page: 10 / 31 all rights strictly reserved. any portion of this pap er shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. 3.3 suggested application circuit 3.3.1 suggested application circuit (vcom dc adjusted by variable resistance) vddio v8 v9 vcomh2 vdd2 vgh v7 vlout3 vcl v10 vdd3 vlout2 v4 v6 v3 v1 v11 v2 vdda vdd vdd_25v vcoml2 v12 v5 vgl g2 r5 r0 vdd b3 r7 g5 g0 r1 b0 r4 b4 g4 g7 g3 b7 b1 g1 b6 r3 b2 r2 g6 gnd r6 b5 vddio vdda vdd_25v gnd vdd2 v1 vlout2 vlout3 v5 frp v7 vgh vgl vcom v4 vdd3 v11 v8 vcomh v10 v3 v9 vcl vcoml v12 v2 v6 vcom vsync grb hsy nc scl dclk cs sda vled- drv gnd gnd vled+ vdd frp vcom vdd drv vled- vled+ l2 bead r1 20k 1 3 2 r5 4.7k c19 4.7u/6v j1 51338 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 c3 2.2u/6v c7 4.7u/10v c6 2.2u/6v c2 4.7u/6v c14 4.7u/25v c11 4.7u/16v c8 4.7u/10v c16 4.7u/16v c9 2.2u/6v c5 4.7u/10v c1 4.7u/6v c4 4.7u/10v c13 4.7u/6v c10 4.7u/6v c12 2.2u/6v c15 2.2u/6v c18 2.2u/6v c17 4.7u/6v c20 10uf q1 fmmt618 r4 1k c22 1nf sb07 d1 l1 33uh r6 30 r2 10k c21 10uf c23 10uf r3 nc 16v 6v gnd www.datasheet.co.kr datasheet pdf - http://www..net/
version: 0.5 page: 11 / 31 all rights strictly reserved. any portion of this pap er shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. 3.3.2 suggested application circuit (vcom dc adjusted by serial control interface) vddio v8 v9 vcomh2 vdd2 vgh v7 vlout3 vcl v10 vdd3 vlout2 v4 v6 v3 v1 v11 v2 vdda vdd vdd_25v vcoml2 v12 v5 vgl g2 r5 r0 vdd b3 r7 g5 g0 r1 b0 r4 b4 g4 g7 g3 b7 b1 g1 b6 r3 b2 r2 g6 gnd r6 b5 vddio vdda vdd_25v gnd vdd2 v1 vlout2 vlout3 v5 frp v7 vgh vgl vcom v4 vdd3 v11 v8 vcomh v10 v3 v9 vcl vcoml v12 v2 v6 vcom vsy nc grb hsy nc scl dclk cs sda vled- drv gnd gnd vled+ vdd frp vcom vdd vled+ drv vled- l2 bead r5 nc r1 nc 1 3 2 c19 4.7u/6v j1 51338 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 c3 2.2u/6v c7 4.7u/10v c6 2.2u/6v c2 4.7u/6v c16 4.7u/16v c8 4.7u/10v c11 4.7u/16v c14 4.7u/25v c4 4.7u/10v c1 4.7u/6v c5 4.7u/10v c9 2.2u/6v c10 4.7u/6v c13 4.7u/6v c12 2.2u/6v c15 2.2u/6v c18 2.2u/6v c17 4.7u/6v c20 10uf sb07 d1 q1 fmmt618 r4 1k c22 1nf r6 30 l1 33uh c21 nc r2 nc c23 10uf r3 0 ohm 16v 6v gnd www.datasheet.co.kr datasheet pdf - http://www..net/
version: 0.5 page: 12 / 31 all rights strictly reserved. any portion of this pap er shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. 3.4 ac timing 3.4.1 timing diagram 3.4.1.1 vertical timing of input 3.4.1.2 horizontal timing of input t vd t v t vf t vb t vp vsync hsync data line 1 line 2 line 3 line 4 line 5 line 272 line 271 line 270 line 269 t vd t v t vf t vb t vp vsync hsync data line 1 line 2 line 3 line 4 line 5 line 272 line 271 line 270 line 269 t hp t hd t hf hsync dclk t h (l1~l272) r1 r2 r3 r4 r5 r480 r479 b1 b2 b3 b4 b5 b480 b479 b478 b477 b476 g1 g2 g3 g4 g5 g480 g479 r477 r478 g477 g478 g476 r476 r [7:0] g [7:0] b [7:0] t hb de t c t hp t hd t hf hsync dclk t h (l1~l272) r1 r2 r3 r4 r5 r480 r479 b1 b2 b3 b4 b5 b480 b479 b478 b477 b476 g1 g2 g3 g4 g5 g480 g479 r477 r478 g477 g478 g476 r476 r [7:0] g [7:0] b [7:0] t hb de t c www.datasheet.co.kr datasheet pdf - http://www..net/
version: 0.5 page: 13 / 31 all rights strictly reserved. any portion of this pap er shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. 3.4.2 timing condition 3.4.2.1. timing parameters parameter symbol min. typ. max. unit. remark frequency 1/tc -- 9.2 10 mhz high time tch 40 -- -- ns clock low time tcl 40 -- -- ns setup time tds 10 -- -- ns data hold time tdh 3 -- -- ns setup time tdes 10 -- -- ns de hold time tdeh 3 -- -- ns frame frequency cycle tv 16.7 ms cycle tv -- 288 -- h display period tvd 272 h front porch tvf 2 4 h pulse width tvp 1 10 h 1 frame scanning time back porch tvb 2 2 h cycle th 494 533 545 dclk display period thd 480 dclk front porch thf 2 8 dclk pulse width thp 1 41 dclk 1 line scanning time back porch thb 2 4 dclk 3.5 power on/off sequence the register disp setting of standby mode disabling / enabling is used to contr ol the build-in power on / off sequence. 3.5.1 power-on (display on; standby disabling) the lcd driver is in default standby mode after vdd/vddio power-on, and set t he register disp to high to disable the standby mode is required for normal operation. when the standb y mode is disabled, a build-in power on sequence is started. the driver ic analog power vd d2 is turned on first, and then the lcd positive and negative power supplies vgh/vgl are pum ped, and followed by the led power. since we recommend using external led driver, the backlight power should be provided at this time. please refer to power on sequence for the detail timing. www.datasheet.co.kr datasheet pdf - http://www..net/
version: 0.5 page: 14 / 31 all rights strictly reserved. any portion of this pap er shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. power-on sequence www.datasheet.co.kr datasheet pdf - http://www..net/
version: 0.5 page: 15 / 31 all rights strictly reserved. any portion of this pap er shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. 3.5.2 power-off (display off; standby enabling) when the register disp is set to low to enable standby mode, a build-in power off sequence is started. please also refer to the power off sequence for the detail timing. vsync vdd2,vgh,vgl normal black black dac output frp output = 0v disp 2 frames 2 frames vgh,vgl=0v source driver output =0v after vgh & vgl=0v 1 frame vled vddio , vdd ltps control signal vsync vdd2,vgh,vgl normal black black dac output frp output = 0v disp 2 frames 2 frames vgh,vgl=0v source driver output =0v after vgh & vgl=0v 1 frame vled vddio , vdd ltps control signal power-off sequence www.datasheet.co.kr datasheet pdf - http://www..net/
version: 0.5 page: 16 / 31 all rights strictly reserved. any portion of this pap er shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. 3.5.3 low-voltage reset following figure suggests for low voltage reset function on power on sequence. when low voltage reset function enable, all the registers are loaded to default setting. a. the rising time (10%-90%) of vdd nedds larger than 1ms. b. after power off, vdd needs to be keep under 0.5v more than 500ms, then it can be power on again. vd < 0.5v > > power power www.datasheet.co.kr datasheet pdf - http://www..net/
version: 0.5 page: 17 / 31 all rights strictly reserved. any portion of this pap er shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. 3.6 serial control setting 3.6.1 input timing specifications (refer to fig. 1) parameter symbol min. typ. max. unit. remark serial load input setup time t s0 50 ns serial load input hold time t h0 50 ns serial data input setup time t s1 50 ns serial data input hold time t h1 50 ns t wl1 50 ns scl pulse width t wh1 50 ns cs pulse width t w2 400 ns scl sda cs 50 50 50 50 s0 t s t s t h0 t h1 t wl1 t wh1 t w2 s1 s15 fig.1 serial interface control timing d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 a2 a3 a4 a5 a6 d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 a2 a3 a4 a5 a6 cs sda scl 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 w r / www.datasheet.co.kr datasheet pdf - http://www..net/
version: 0.5 page: 18 / 31 all rights strictly reserved. any portion of this pap er shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. 3.6.2 serial setting table register address register data (default setting) no w r / a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 r0 0 0 0 0 0 0 0 0 x vdir(1) hdir(1) 0 vcom_ac(0110) r1 0 0 0 0 0 0 0 1 0 vcom_dc(40h) r2 0 0 0 0 0 0 1 0 contrast(40h) r3 0 0 0 0 0 0 1 1 x sub-contrast_r(40h) r4 0 0 0 0 0 1 0 0 x sub-contrast_b(40h) r5 0 0 0 0 0 1 0 1 brightness(40h) r6 0 0 0 0 0 1 1 0 x sub-brightness_r(40h) r7 0 0 0 0 0 1 1 1 x sub-brightness_b(40h) r8 0 0 0 0 1 0 0 0 hsync blanking(2bh) r9 0 0 0 0 1 0 0 1 vdpol(1) hdpol(1) vsync blanking(0ch) r10 0 0 0 0 1 0 1 0 1 dclkpol(1) 0 0 1 0 1 0 r11 0 0 0 0 1 0 1 1 led_current(00) bl_drv(00) drv_freq(00) pfm_duty(10) r12 0 0 0 0 1 1 0 0 led_on_cycle(0111) led_on_ratio(1111) r13 0 0 0 0 1 1 0 1 x 1 x x grb(1) 1 shdb1(0) disp(0) r64 0 1 0 0 0 0 0 0 1 1 0 x 00 00 r66 0 1 0 0 0 0 1 0 x 43h r68 0 1 0 0 0 1 0 0 x 28h note: x is dont care. could be registered by customer. register r0 vcom_ac : common voltage ac level selection (deviati on 0.1v) frp output vcom_ac frp output vcom_ac x 1 0 1 0 1 0 1 0 1 0 1 0 d0 x 1 1 0 0 1 1 0 0 1 1 0 0 d1 1 0 0 0 0 1 1 1 1 0 0 0 0 d2 6.8 1 7.0 1 6.9 1 6.6 1 6.5 0 6.3 0 6.2 0 6.0 0 5.9 0 6.4 (default) 0 d3 6.1 0 6.7 1 5.8 0 voltage (v) vcom_ac x 1 0 1 0 1 0 1 0 1 0 1 0 d0 x 1 1 0 0 1 1 0 0 1 1 0 0 d1 1 0 0 0 0 1 1 1 1 0 0 0 0 d2 6.8 1 7.0 1 6.9 1 6.6 1 6.5 0 6.3 0 6.2 0 6.0 0 5.9 0 6.4 (default) 0 d3 6.1 0 6.7 1 5.8 0 voltage (v) vcom_ac vcom_ac 0 hdir vdir 0 x 00h address r0 d0 d1 d2 d3 d4 d5 d6 d7 register vcom_ac 0 hdir vdir 0 x 00h address r0 d0 d1 d2 d3 d4 d5 d6 d7 register w r / www.datasheet.co.kr datasheet pdf - http://www..net/
version: 0.5 page: 19 / 31 all rights strictly reserved. any portion of this pap er shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. register r1 vcom_dc gnd frp output vcom_dc gnd frp output : : : : d6~d0 2.605 (default) 40h 3.2 7fh 2 00h voltage (v) vcom_dc : : : : d6~d0 2.605 (default) 40h 3.2 7fh 2 00h voltage (v) vcom_dc vcom_dc 0 0 01h address r1 d0 d1 d2 d3 d4 d5 d6 d7 register vcom_dc 0 0 01h address r1 d0 d1 d2 d3 d4 d5 d6 d7 register w r / vcom_dc : common voltage dc level selection vcom_ac 0 hdir vdir 0 x 00h address r0 d0 d1 d2 d3 d4 d5 d6 d7 register vcom_ac 0 hdir vdir 0 x 00h address r0 d0 d1 d2 d3 d4 d5 d6 d7 register w r / hdir : horizontal shift direction setting shift from left to right, ex : first data = y1 y2y1439 y1440 = last data (default) 1 shift from right to left, ex : last data = y1 y2y1439 y1440 = first data 0 description hdir shift from left to right, ex : first data = y1 y2y1439 y1440 = last data (default) 1 shift from right to left, ex : last data = y1 y2y1439 y1440 = first data 0 description hdir shift from up to down, ex : first line = l1 l2l271 l272 = last line (default) 1 shift from down to up, ex : last line = l1 l2l271 l272 = first line 0 description vdir shift from up to down, ex : first line = l1 l2l271 l272 = last line (default) 1 shift from down to up, ex : last line = l1 l2l271 l272 = first line 0 description vdir vdir : vertical shift direction setting www.datasheet.co.kr datasheet pdf - http://www..net/
version: 0.5 page: 20 / 31 all rights strictly reserved. any portion of this pap er shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. register r2, r3, r4, r5, r6, r7 d7~d0 center (0) (default) 40h bright ( +191 ) ffh dark ( -64 ) 00h setting brightness d7~d0 center (0) (default) 40h bright ( +191 ) ffh dark ( -64 ) 00h setting brightness sub-brightness_rb : rb sub-brightness level setting, setting accuracy : 1 step / bit d6~d0 center (0) (default) 40h bright ( +63 ) 7fh dark ( -64 ) 00h setting sub-brightness d6~d0 center (0) (default) 40h bright ( +63 ) 7fh dark ( -64 ) 00h setting sub-brightness 0 brightness 05h address r5 d0 d1 d2 d3 d4 d5 d6 d7 register 0 brightness 05h address r5 d0 d1 d2 d3 d4 d5 d6 d7 register w r / sub-brightness_r 0 x 06h address r6 d0 d1 d2 d3 d4 d5 d6 d7 register sub-brightness_r 0 x 06h address r6 d0 d1 d2 d3 d4 d5 d6 d7 register w r / sub-brightness_b 0 x 07h address r7 d0 d1 d2 d3 d4 d5 d6 d7 register sub-brightness_b 0 x 07h address r7 d0 d1 d2 d3 d4 d5 d6 d7 register w r / brightness : rgb bright level setting, setting accur acy : 1 step / bit contrast : rgb contrast level setting, the gain chan ges (1/64) / bit d7~d0 1 (default) 40h 3.984 ffh 0 00h gain contrast d7~d0 1 (default) 40h 3.984 ffh 0 00h gain contrast sub-contrast_rb : rb sub-contrast level setting, the gain changes (1/256) / bit d6~d0 1 (default) 40h 1.246 7fh 0.75 00h gain sub-contrast d6~d0 1 (default) 40h 1.246 7fh 0.75 00h gain sub-contrast 0 contrast 02h address r2 d0 d1 d2 d3 d4 d5 d6 d7 register 0 contrast 02h address r2 d0 d1 d2 d3 d4 d5 d6 d7 register w r / sub-contrast_r 0 x 03h address r3 d0 d1 d2 d3 d4 d5 d6 d7 register sub-contrast_r 0 x 03h address r3 d0 d1 d2 d3 d4 d5 d6 d7 register w r / sub-contrast_b 0 x 04h address r4 d0 d1 d2 d3 d4 d5 d6 d7 register sub-contrast_b 0 x 04h address r4 d0 d1 d2 d3 d4 d5 d6 d7 register w r / www.datasheet.co.kr datasheet pdf - http://www..net/
version: 0.5 page: 21 / 31 all rights strictly reserved. any portion of this pap er shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. contrast gain=0~3.984 brightness -64~+191 dout[7:0] din[7:0] contrast[7:0] sub-contrast r/b gain=0.75~1.246 sub-brightness r/b -64~+63 sub-contrast r[6:0] sub-contrast b[6:0] bright[7:0] sub-bright r[6:0] sub-bright b[6:0] 12 bit operation d7~d0 43 (default) 2bh 0 00h 255 ffh dclk hsync blanking d7~d0 43 (default) 2bh 0 00h 255 ffh dclk hsync blanking hsync width t h s w h blanking t hb h display t hd h front porch t h fp hsync dclk 1 h t h r [7:0] g [7:0] b [7:0] h back porch t h bp hsync blanking : horizontal blanking setting 0 hsync blanking 08h address r8 d0 d1 d2 d3 d4 d5 d6 d7 register 0 hsync blanking 08h address r8 d0 d1 d2 d3 d4 d5 d6 d7 register w r / www.datasheet.co.kr datasheet pdf - http://www..net/
version: 0.5 page: 22 / 31 all rights strictly reserved. any portion of this pap er shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. d5~d0 12 (default) 0ch 63 3fh 0 00h h vsync blanking d5~d0 12 (default) 0ch 63 3fh 0 00h h vsync blanking valid data v display t vd v blanking t vb 1 fra me v front porch t vfp v back porch t vbp vsync width t vsw vsync hsync data valid data v display t vd v blanking t vb 1 fra me v front porch t vfp v back porch t vbp vsync width t vsw vsync hsync data vsync blanking : vertical blanking setting vsync blanking hdpol 0 vdpol 09h address r9 d0 d1 d2 d3 d4 d5 d6 d7 register vsync blanking hdpol 0 vdpol 09h address r9 d0 d1 d2 d3 d4 d5 d6 d7 register w r / hdpol : hsync polarity selection negative polarity (default) 1 positive polarity 0 function hdpol negative polarity (default) 1 positive polarity 0 function hdpol vdpol : vsync polarity selection negative polarity (default) 1 positive polarity 0 function vdpol negative polarity (default) 1 positive polarity 0 function vdpol vsync blanking hdpol 0 vdpol 09h address r9 d0 d1 d2 d3 d4 d5 d6 d7 register vsync blanking hdpol 0 vdpol 09h address r9 d0 d1 d2 d3 d4 d5 d6 d7 register w r / dclkpol : dclk polarity selection negative polarity (default) 1 positive polarity 0 description dclkpol negative polarity (default) 1 positive polarity 0 description dclkpol when the command is sent to asic, it will be execute d immediately. 0 0 0 1 1 0 dclkpol 0 1 0ah address r10 d0 d1 d2 d3 d4 d5 d6 d7 register 0 0 0 1 1 0 dclkpol 0 1 0ah address r10 d0 d1 d2 d3 d4 d5 d6 d7 register w r / www.datasheet.co.kr datasheet pdf - http://www..net/
version: 0.5 page: 23 / 31 all rights strictly reserved. any portion of this pap er shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. vsync hsync vsync hsync ? hdpol=1, vdpol=1, clkpol=1 ? hdpol=0, vdpol=0, clkpol=0 d1 d2 d3 d4 data data d1 d2 d3 d4 dclk dclk vsync hsync vsync hsync ? hdpol=1, vdpol=1, clkpol=1 ? hdpol=0, vdpol=0, clkpol=0 d1 d2 d3 d4 data data d1 d2 d3 d4 dclk dclk dclk dclk pfm_duty : pfm duty cycle selection for back light po wer converter note 22/32 21/32 19/32 16/32 pfm duty cycle d0 d1 70 % 65 % (default) 60 % 50 % 1 0 1 0 1 0 0 1 pfm_duty note 22/32 21/32 19/32 16/32 pfm duty cycle d0 d1 70 % 65 % (default) 60 % 50 % 1 0 1 0 1 0 0 1 pfm_duty dclk / 256 1 1 dclk / 128 0 1 d2 d3 1 0 drv_freq frequency dclk / 64 dclk / 32 (default) 0 0 dclk / 256 1 1 dclk / 128 0 1 d2 d3 1 0 drv_freq frequency dclk / 64 dclk / 32 (default) 0 0 led_current bl_drv drv_freq pfm_duty 0 0bh address r11 d0 d1 d2 d3 d4 d5 d6 d7 register led_current bl_drv drv_freq pfm_duty 0 0bh address r11 d0 d1 d2 d3 d4 d5 d6 d7 register w r / drv_freq : drv signal frequency setting www.datasheet.co.kr datasheet pdf - http://www..net/
version: 0.5 page: 24 / 31 all rights strictly reserved. any portion of this pap er shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. bl_drv : backlight driving capability setting capability d4 d5 bl_drv 1 0 1 0 12 times the normal capability 1 8 times the normal capability 1 4 times the normal capability normal capability (default) 0 0 capability d4 d5 bl_drv 1 0 1 0 12 times the normal capability 1 8 times the normal capability 1 4 times the normal capability normal capability (default) 0 0 d6 d7 dc-dc feedback voltage led_current 1 0 1 0 0.3v (10ma) 1 0.45v (15ma) 1 0.75v (25ma) 0.6 v (default, 20ma) 0 0 d6 d7 dc-dc feedback voltage led_current 1 0 1 0 0.3v (10ma) 1 0.45v (15ma) 1 0.75v (25ma) 0.6 v (default, 20ma) 0 0 led_current bl_drv drv_freq pfm_duty 0 0bh address r11 d0 d1 d2 d3 d4 d5 d6 d7 register led_current bl_drv drv_freq pfm_duty 0 0bh address r11 d0 d1 d2 d3 d4 d5 d6 d7 register w r / led_current : adjust led current led_on_ratio 0 led_on_cycle 0ch address r12 d0 d1 d2 d3 d4 d5 d6 d7 register led_on_ratio 0 led_on_cycle 0ch address r12 d0 d1 d2 d3 d4 d5 d6 d7 register w r / 16 / 16 (default) 1 1 1 1 15 / 16 0 1 1 1 14 / 16 1 0 1 1 13 / 16 0 0 1 1 12 / 16 1 1 0 1 11 / 16 0 1 0 1 10 / 16 1 0 0 1 9 / 16 0 0 0 1 1 1 1 1 0 0 0 0 d2 led_on_ratio 0 0 0 0 0 0 0 0 d3 8 / 16 1 1 6 / 16 1 0 4 / 16 1 1 3 / 16 0 1 0 0 1 0 d0 d1 7 / 16 1 5 / 16 0 2 / 16 0 value 1 / 16 0 16 / 16 (default) 1 1 1 1 15 / 16 0 1 1 1 14 / 16 1 0 1 1 13 / 16 0 0 1 1 12 / 16 1 1 0 1 11 / 16 0 1 0 1 10 / 16 1 0 0 1 9 / 16 0 0 0 1 1 1 1 1 0 0 0 0 d2 led_on_ratio 0 0 0 0 0 0 0 0 d3 8 / 16 1 1 6 / 16 1 0 4 / 16 1 1 3 / 16 0 1 0 0 1 0 d0 d1 7 / 16 1 5 / 16 0 2 / 16 0 value 1 / 16 0 led_on_ratio : set the active ratio of enable signal, and we can u se it to decrease the brightness of the leds. the advantage of this function is that it has 16Cstep to fi ne tune the brightness. if you would not like to decrease the brightness of the backlight, please set to 1111. (please refer to the example in the following page.) www.datasheet.co.kr datasheet pdf - http://www..net/
version: 0.5 page: 25 / 31 all rights strictly reserved. any portion of this pap er shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. led_on_ratio 0 led_on_cycle 0ch address r12 d0 d1 d2 d3 d4 d5 d6 d7 register led_on_ratio 0 led_on_cycle 0ch address r12 d0 d1 d2 d3 d4 d5 d6 d7 register w r / 16 1 1 1 1 15 0 1 1 1 14 1 0 1 1 13 0 0 1 1 12 1 1 0 1 11 0 1 0 1 10 1 0 0 1 9 0 0 0 1 1 1 1 1 0 0 0 0 d6 led_on_cycle 0 0 0 0 0 0 0 0 d7 8 (default) 1 1 6 1 0 4 1 1 3 0 1 0 0 1 0 d4 d5 7 1 5 0 2 0 value 1 0 16 1 1 1 1 15 0 1 1 1 14 1 0 1 1 13 0 0 1 1 12 1 1 0 1 11 0 1 0 1 10 1 0 0 1 9 0 0 0 1 1 1 1 1 0 0 0 0 d6 led_on_cycle 0 0 0 0 0 0 0 0 d7 8 (default) 1 1 6 1 0 4 1 1 3 0 1 0 0 1 0 d4 d5 7 1 5 0 2 0 value 1 0 led_on_cycle : set the cycle of enable signal. need to keep the frequency of the enable signal more than 120 hz to prevent the backlight twinkle visible. (please refer to the example in the following page.) enable signal disable enable hsync drv cycle 16 led_on_cycle led_on_cycle (led_on_ratio 16 ) led_on_cycle (16 led_on_ratio 16) (cycle) (enable) (disable) unit : hsync for example: led_on_ratio is 1001 , and led_on_cycle is 0111 , then: cycle = 16 8 = 128(hsync) enable = 8 (( 10/16 ) 16) = 80(hsync) disable = 8 (16-( 10/16 ) 16) = 48(hsync) 62.5% on www.datasheet.co.kr datasheet pdf - http://www..net/
version: 0.5 page: 26 / 31 all rights strictly reserved. any portion of this pap er shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. the back light power converter is controlled by stbs power on/off sequence 1 the back light power converter is off (default) 0 description shdb1 the back light power converter is controlled by stbs power on/off sequence 1 the back light power converter is off (default) 0 description shdb1 shdb1 : shut down for back light power converter normal operation (display on), with power on/off sequen ce 1 standby (display off); timing control, dac, and dc/dc c onverter are off, and register data should be kept (default) 0 description disp normal operation (display on), with power on/off sequen ce 1 standby (display off); timing control, dac, and dc/dc c onverter are off, and register data should be kept (default) 0 description disp disp : standby (power saving) mode setting note : in standby mode, source driver output =0v, v gh =0v, vgl =0v, frp =0v x x 1 disp shdb1 1 grb 0 x 0dh address r13 d0 d1 d2 d3 d4 d5 d6 d7 register x x 1 disp shdb1 1 grb 0 x 0dh address r13 d0 d1 d2 d3 d4 d5 d6 d7 register w r / grb : register reset setting normal operation (default) 1 reset all registers to default value 0 description grb normal operation (default) 1 reset all registers to default value 0 description grb www.datasheet.co.kr datasheet pdf - http://www..net/
version: 0.5 page: 27 / 31 all rights strictly reserved. any portion of this pap er shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. 3.6.3 suggested serial command settings: power off vsync / hsync / dclk / data input >10us input data 0d4ch register : r13 standby (display off) vdd, vddio power on vsync / hsync / dclk / data input >100us register : vdd, vddio input data 0d44h r13 global reset 0b06h back light efficiency optimization r11 r13 0d4dh disable standby 0d4fh back light on r13 40c0h pre-charge on r64 4243h pre-charge width optimization r66 4428h switch active period time optimization r66 power on vsync / hsync / dclk / data input >100us register : vdd, vddio input data 0d44h r13 global reset 0b06h back light efficiency optimization r11 r13 0d4dh disable standby 0d4fh back light on r13 40c0h pre-charge on r64 4243h pre-charge width optimization r66 4428h switch active period time optimization r66 www.datasheet.co.kr datasheet pdf - http://www..net/
version: 0.5 page: 28 / 31 all rights strictly reserved. any portion of this pap er shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. 4. optical specification item symbol condition min. typ. max. unit remark response time rise fall tr tf =0 - - 20 20 40 40 ms ms note 4 contrast ratio cr at optimized viewing 250 500 - note 6, 7 viewing angle top bottom left right cr R 10 70 70 70 70 80 80 80 80 - - - deg . note 8 brightness y l =0 200 300 - cd/m 2 note 9 x =0 0.27 0.32 0.37 white chromaticity y =0 0.31 0.36 0.41 note 1: measurement is in the dark room, optical ambient temperature =25 , and backlight current i l =20 ma note 2: to be measured in the dark room. note 3:to be measured on the center area of panel with a field angle of 1by topcon luminance meter bm-7, after 10 minutes operation. note 4: definition of response time: the output signals of photo detector are measured when the input signals are changed from black to white(falling time) and from white to black(rising t ime), respectively. note 5. from liquid crystal characteristics, response time will become slower and the color of panel will become darker when ambient temperature is below 25 . note 6. definition of contrast ratio: contrast ratio is calculated with the following formula. photo detector output when lcd is at white state photo detector output when lcd is at black state note 7. white vi=v i50 1.5v black vi=v i50 2.0v means that the analog input signal swings in phase with com signal. means that the analog input signal swings out of phase with com signal. contrastratio (cr)= www.datasheet.co.kr datasheet pdf - http://www..net/
version: 0.5 page: 29 / 31 all rights strictly reserved. any portion of this pap er shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. v i50 : the analog input voltage when transmission is 50% the 100% transmission is defined as the transmission of lcd panel when all the input terminals of module are electrically opened. note 8. definition of viewing angle: refer to figure as below. note 9. measured at the center area of the panel when all the input terminals of lcd panel are electrically opened. www.datasheet.co.kr datasheet pdf - http://www..net/
version: 0.5 page: 30 / 31 all rights strictly reserved. any portion of this pap er shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. 5. absolute ratings of ambient environment no. test items conditions remark 1 high temperature storage ta= 80 240hrs 2 low temperature storage ta= -25 240hrs 3 high ttemperature operation ta= 60 240hrs 4 low temperature operation ta= 0 240hrs 5 high temperature & high ta= 60 . 90% rh 240hrs operation 6 heat shock -25 ~80 , 50 cycle, 2hrs/cycle non-operation 7 electrostatic discharge 200v,200pf(0 ), once for each terminal non-operation frequency range : 10~55hz stoke : 1.5mm sweep : 10~55hz~10hz 2 hours for each direction of x,y,z 8 vibration (6 hours for total) non-operation jis c7021, a-10 condition a 9 mechanical shock 100g . 6ms, x, y, z 3 times for each direction non-operation jis c7021, a-7 condition c 10 vibration (with carton) random vibration: 0.015g 2 /hz from 5~200hz C6db/octave from 200~500hz iec 68-34 11 drop (with carton) height: 60cm 1 corner, 3 edges, 6 surfaces note 1 : ta: ambient temperature. note 2: in the standard condition, there is not display func tion ng issue occurred. all the cosmetic specification is judged before the reliability stress. www.datasheet.co.kr datasheet pdf - http://www..net/
version: 0.5 page: 31 / 31 all rights strictly reserved. any portion of this pap er shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. 6. packing form www.datasheet.co.kr datasheet pdf - http://www..net/

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